νMOS Enhanced Differential Current-Switch Threshold Logic Gates
نویسندگان
چکیده
This paper presents a way to enhance the Differential Current-Switch Threshold Logic gate (DCSTL) in order to allow the gate to perform more complex functions. This enhancement is achieved by replacing the MOS-transistors at the dataand threshold mapping bank of the DCSTL gate with neuronMOS transisors. First, we introduce the neuronMOS-enhanced DCSTL gate. Then, the results of HSPICE simulations of a 7-input parity and a 3-bit addition function implemented with the enhanced DCSTL gate is presented, along with a comparison with the same functions implemented using the original DCSTL gate. These simulations indicate that the designs based on enhanced DCSTL gates can achieve a 12.5% speed-up over the conventional DCSTL gate designs for both addition and parity. HSPICE power estimations also suggest that the standard DCSTL gate dissipates 30% more power when performing a 7-bit parity, and 5% in the case of a 3-bit addition. Keywords—Threshold logic, neuron-MOS transistors, parity, addition
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